A look at TSMC's process node roadmap for 2025 and 2026

2024-04-18

TSMC's N3X, N2P, and A16 process nodes are set to be introduced in 2025 and 2026.

As TSMC announced last week, the company will begin high-volume manufacturing using the N3P fabrication process later this year, which will be the company's most advanced node for some time. Things will get more interesting next year, as TSMC will have two process technologies that can actually compete with each other when they enter high-volume manufacturing (HVM) in the second half of 2025.

TSMC stated that compared to N3P, chips manufactured with N3X can reduce power consumption by 7% at the same frequency by reducing Vdd from 1.0V to 0.9V, improve performance by 5% at the same area, or increase transistor density by 10% at the same frequency. At the same time, the main advantage of N3X over its predecessor is its maximum voltage of 1.2V, which is very important for high-performance applications such as desktop or data center GPUs.

TSMC's N2 will be TSMC's first production node to use gate-all-around (GAA) nanosheet transistors, which will significantly enhance its performance, power consumption, and area (PPA) characteristics. Compared to N3E, semiconductors produced by N3 can reduce power consumption by 25% - 30% (at the same number of transistors and frequency), increase performance by 10% - 15% (at the same number of transistors and power), and increase transistor density by 15% (at the same speed and power).

Although TSMC is undoubtedly the undisputed champion in terms of power consumption and transistor density with N2, in terms of performance, N3X may challenge it, especially at high voltages. For many customers, N3X will also benefit from the use of proven FinFET transistors, so N2 may not become TSMC's best node in the second half of 2025.2026 Year: N2P and A16

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Next year, TSMC will once again offer nodes targeted at smartphones and high-performance computing applications: N2P (Performance-enhanced 2-nanometer) and A16 (1.6-nanometer with backside power supply).

Compared to the original N2, N2P is expected to reduce power consumption by 5% - 10% (at the same speed and number of transistors) or improve performance by 5% - 10% (at the same power and number of transistors). At the same time, compared with N2P, A16 reduces power consumption by 20% (at the same speed and number of transistors), improves performance by 10% (at the same power and number of transistors), and increases transistor density by 10%.

Please remember that A16 has an enhanced backside power supply network, so it is likely to become the preferred node for chip designers who focus on performance. Of course, using A16 will be more expensive because the backside power supply requires additional process steps.

 

TSMC Launches "Global Wafer Fabs Replication Plan"

TSMC also revealed some details of its global super wafer fab manufacturing plan, which is the company's strategy to replicate its manufacturing processes at its multiple super wafer fab sites.

At present, it is well documented that large multinational wafer fabs need a set of processes to replicate their facilities. Chip manufacturers need to be able to quickly transplant new and updated manufacturing processes to other factories to achieve the necessary output and avoid multi-quarter bottlenecks caused by the need to readjust the wafer fab.

While Intel has a famous "exact replication" plan, which is one of the company's main competitive advantages, it allows it to share the details of manufacturing processes between wafer fabs around the world to maximize output and reduce performance variability. Meanwhile, as TSMC expands its capacity around the world, the company is also in urgent need of a similar project to quickly maximize output and productivity at its new fabs in Japan and the United States.

As mentioned at last year's symposium, "Global Gigafab Manufacturing" is a powerful global manufacturing and management platform. Wang Yaolong, Vice President of TSMC's wafer fab operations, said, "We have achieved one-stop management of the wafer fab to ensure consistent operational efficiency and production quality of our Gigafab worldwide. In addition, we are also pursuing sustainable development worldwide, including green manufacturing, global talent training, supply chain localization, and social responsibility."When it comes to the improvement of manufacturing technology, there are primarily two main mechanisms: Continuous Process Improvement (CPI) for increasing output, and Statistical Process Control (SPC) for reducing performance variability. To this end, the company has a variety of internal technologies that rely on process control based on machine learning, continuous quality measurement, and various productivity enhancement methods. With global Gigafab manufacturing, TSMC can improve yield and performance worldwide by sharing knowledge between different sites through CPI and SPC.

"Whether it's the setup of the wafer factory or the process control system, everything is essentially replicated from the Taiwan factory," said Kevin Zhang, Senior Vice President of Business Development and Overseas Operations Office, and Deputy Co-Chief Operating Officer.

TSMC has not yet started producing chips in its wafer factories in Germany, Japan, and the United States. Therefore, it remains to be seen how quickly the yield of the wafer factory Fab 23 (located in Kumamoto, Japan) and Fab 21 (located in Arizona) will increase to the level of Taiwan when they start operation in 2024 and 2025, respectively. However, with the implementation of the global super wafer factory manufacturing plan, this goal may be achieved soon.

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