FOPLP, widely popular

2024-06-11

The semiconductor industry, as the cornerstone of modern electronic technology, has been providing a constant source of momentum for the performance improvement and cost reduction of electronic products. With the increasing complexity of chip design and the enhancement of system integration, the increase in wiring density has become an inevitable trend. At the same time, with the rapid development of technologies such as the Internet of Things, cloud computing, and big data, the demand for communication and data transmission between devices has also shown explosive growth. The increase in I/O port requirements has become another key factor driving the development of semiconductor technology.

Under such circumstances, traditional packaging technologies can no longer meet the growing performance and integration requirements. Therefore, the semiconductor industry is constantly exploring new packaging technologies to cope with the challenges brought about by the increase in wiring density and the demand for I/O ports. Fan-out packaging, as an advanced packaging technology, is gradually becoming the new favorite in the field of semiconductor packaging due to its unique advantages.

01

Features of Fan-out Packaging

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Smaller Size: Fan-out packaging does not require a packaging substrate, thus meeting the demand for thin packaging. Through fan-out packaging technology, different chips can be integrated into a single two-dimensional packaging body, achieving thin-sized System in Package (SiP) packaging technology, which changes the original method of using Through-Silicon Vias (TSV) to vertically stack multiple chips.

Stronger Performance: Under the same chip size, fan-out packaging can achieve a wider range and more layers of Redistribution Layer (RDL). With the increase in the number of RDL layers, the number of I/O pins on the chip also increases. Various chips with different functions are integrated into a single packaging body through the connection of RDL, making their functionality even stronger.

Lower Cost: The packaging body produced using fan-out packaging technology can significantly shorten the complex process and reduce the use of materials, thereby effectively reducing production costs and achieving the advantage of low cost.

Fan-out packaging is mainly divided into two types: Fan-Out Wafer Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP).

As an emerging technology for heterogeneous integration packaging, fan-out packaging technology has developed to the panel level, which can be produced on a larger area, achieving the goal of further reducing production costs while meeting the market's demand for chip performance. It is becoming the most promising technological platform in advanced packaging technology that can provide heterogeneous integration while reducing production costs.Let's take a closer look at the specific advantages of FOPLP over FOWLP and the application fields they are each suitable for.

02

The Competition Between FOWLP and FOPLP

FOWLP is a type of Wafer Level Packaging (WLP). The difference between WLP and traditional packaging lies in the order of wafer cutting and packaging. In the traditional packaging process, packaging is carried out after the wafer is cut into individual chips, while wafer-level packaging is done by packaging first and then cutting.

Let's review WLP. WLP emerged around the year 2000 and comes in two types: Fan-in and Fan-Out. Initially, WLP mostly adopted the Fan-in form, which can be referred to as Fan-in WLP or FIWLP, mainly used for chips with small areas and fewer pins.

With the advancement of IC processes, the chip area has been reduced, and the chip area can no longer accommodate enough pins, thus leading to the development of the Fan-Out WLP packaging form, also known as FOWLP, which fully utilizes the Redistribution Layer (RDL) for connections outside the chip area to obtain more pins.

FOPLP draws on the ideas and technologies of FOWLP but uses a larger panel. Therefore, FOPLP has significant advantages in capacity, efficiency, and cost reduction. Its high area utilization rate effectively reduces waste, and it can process more chips in one packaging process, significantly improving packaging efficiency, forming a strong scale effect, and thus having a very strong cost advantage.

According to a Yole report, for example, the area utilization rate of FOWLP technology is less than 85%, while the area utilization rate of FOPLP is greater than 95%, allowing for more chips to be placed, and the cost is also cheaper than FOWLP; the cost of panel-level packaging will be reduced by 66% compared to wafer-level packaging.

In addition, the choice of substrate materials for FOPLP is also more flexible, allowing for the use of glass substrates or metal substrates.According to a report by Yole, the cost of chip manufacturing gradually decreases with the increase in substrate area. Transitioning from 200mm to 300mm can save about 25% of the cost, while transitioning from 300mm to panel-level packaging can save up to 66% of the cost.

FOPLP and FOWLP each have their own niche directions. FOWLP focuses on packaging directly on the wafer, characterized by small size and high integration, suitable for high-performance, high-density application scenarios, such as the production of large chips like CPUs, GPUs, and FPGAs. FOPLP, on the other hand, provides a larger packaging size and higher production flexibility through packaging at the panel level, meeting a more diverse range of packaging needs. FOPLP focuses on the application of high-power, high-current power semiconductor products, which do not require the most advanced processes and equipment, nor do they require very fine line widths/spacing. It is used in the production of chips such as APE, PMIC, and power devices with an I/O count of about 10-500.

As an important branch of the development of advanced packaging technology, FOPLP is being sought after by many manufacturers.

03

CoWoS shortage, FOPLP ushers in opportunities

The most eye-catching advanced packaging in the market is CoWoS. CoWoS can be seen separately, where CoW (Chip-on-Wafer) refers to chip stacking, and WoS (Wafer-on-Substrate) is the packaging of the stacked chips on the substrate. According to the arrangement, it is divided into 2.5D and 3D, which can not only reduce the space required by the chip but also effectively reduce power consumption, thereby achieving accelerated computing while the cost is still controllable.

With the emergence of ChatGPT, generative AI has become popular worldwide, driving a strong demand for AI chips. NVIDIA's H100 and A100 are all manufactured by TSMC and use TSMC's CoWoS advanced packaging technology. In addition to NVIDIA, AMD MI300 has also introduced CoWoS technology, causing a shortage of CoWoS production capacity.

As a result, many manufacturers have started looking for some other solutions to solve the production capacity problem, which has also brought new opportunities for FOPLP packaging.

Liu Hongjun, deputy general manager of Suzhou Jingfang Semiconductor, said: Due to its process size, FOPLP's technical indicators are weaker than TSMC's CoWoS-S, but its potential advantages are the possibility of cost and production capacity bottleneck breakthroughs. These factors have prompted current CoWoS users to actively seek alternative technologies.

As a rising star in fan-out packaging, FOPLP is attracting attention across the industry with lower costs and greater flexibility. Therefore, FOPLP has also become a choice for many large manufacturers.FOPLP Shines in These Markets

In recent years, the development of AIoT, 5G, autonomous driving, and photovoltaic energy storage industries has greatly driven the demand for power devices, sensor chips, and RF chips in the market.

According to Prismark's forecast, by 2026, 5G & IoT and automotive electronics will be the only two applications that increase market share, accounting for nearly 30% of the total semiconductor revenue. Among them, in the automotive field, with the evolution of the new four modernizations of cars, the number of chips used in a traditional car has been around 500-600, and now the average number of chips required per car has reached 1000-2000. Therefore, automotive chips will become the application category with the highest growth rate of chips.

The rapid development of automotive electronics has made the importance of fan-out packaging increasingly obvious. In a new energy vehicle, 77% of the semiconductor value will be produced in fan-out packaging, and 66% of this can be attributed to FOPLP technology.

In addition, FOPLP relies on precise rerouting layer (RDL) processes to achieve high-speed, high-density interconnections between chips (D2D), which is crucial for AI computing. This feature ensures seamless transmission and efficient processing of massive data flows, directly addressing the pain points of data processing in the AI era. Furthermore, FOPLP has shown obvious advantages in enhancing chip functional integration, reducing interconnection distances, and promoting system design innovation, which coincides with the high-performance, high-integration standards required by the AI era, laying a solid foundation for the future of intelligent computing.

Therefore, from the perspective of the application market, the future prospects of FOPLP technology are broad. The core lies in that, among many advanced packaging technologies, board-level packaging technology has a large production capacity and more cost advantages, and is currently the best solution for the production of high-speed growing power devices, sensors, communication, and other automotive-grade chips.

05

Many Manufacturers Praise

In terms of FOPLP, Samsung is an absolute leader. In 2018, Samsung Electronics achieved a new milestone by launching an APE-PMIC device with fan-out embedded panel-level packaging (ePLP) PoP technology for the Samsung Galaxy Watch. Samsung Electronics continues to innovate cost-effective high-density fan-out packaging to compete with TSMC again in Apple's packaging and front-end business.Last year, Samsung's Device Solutions (DS) division's Advanced Packaging (AVP) business team began developing the use of Fan-Out Panel Level Package (FOPLP) advanced packaging technology for 2.5D chip packaging. Leveraging this technology, Samsung expects to integrate SoC and High Bandwidth Memory (HBM) onto a silicon interposer, further constructing it into a complete chip.

From Samsung's FOPLP-related papers published at international academic conferences, it is evident that Samsung is committed to developing FOPLP advanced packaging technology to overcome the limitations of 2.5D packaging. Therefore, once Samsung successfully applies the FO-PLP advanced packaging technology, it will generate synergistic effects with its wafer foundry and memory businesses. As a result, Samsung is attracting customers by proposing a one-stop solution (Turn-key), which involves producing semiconductors for AI design manufacturers (such as NVIDIA and AMD), coupled with providing HBM and packaging technology to attract customers. Thus, if Samsung becomes competitive in packaging, it will be able to strengthen its semiconductor business. TSMC has exerted a significant influence in the semiconductor foundry market due to its 2.5D advanced packaging. Industry insiders suggest that Samsung may plan to use 2.5D advanced packaging technology to catch up with TSMC.

ASE Technology is also one of the leading manufacturers that first laid out panel-level fan-out technology. The production line was completed at the end of 2019, and mass production began in the second half of 2020, applied in RF, FEM, Power, and Server fields. In 2022, ASE Technology launched the VIPack advanced packaging platform, providing a vertical interconnection integrated packaging solution. VIPack is an advanced interconnection technology solution based on 3D heterogeneous integration, establishing a complete collaborative platform.

In addition, manufacturers such as Powertech Technology and Innolux have invested in the mass production of fan-out panel-level packaging technology, combining their own process capabilities. With the increasing attention to FOPLP, different business model manufacturers have joined the market competition in recent years, including IDM factories, foundries, packaging factories, and even panel factories, PCB factories, etc. They have strongly sensed the opportunity to enter the advanced packaging field through fan-out technology.

Mainland China's fan-out panel-level packaging manufacturers are also taking advantage of the situation, and several manufacturers have already achieved mass production or production capabilities. For example:

Huaxia Microelectronics, ESWIN, Zhongke Sihe, and Tianxin Interconnect have all entered the fan-out panel-level packaging.

Huaxia Microelectronics established the Silpan Microelectronics (Chongqing) company in 2018 to engage in panel-level packaging business. The panel-level packaging technology effectively solves the high cost of Chiplet packaging and is more suitable for heterogeneous integration of power semiconductor packaging. It is reported that Silpan has a world-class team in various aspects such as market, design, equipment, process, and materials in the field of advanced packaging, which can provide customers with a full range of Fan-out packaging technology solutions - ONEIRO packaging.

Chengdu Yicheng Technology Co., Ltd. was established in 2017 and is an incubated enterprise of Beijing Yicheng Technology Group's ecosystem. Its services cover packaging design, chip packaging, and chip testing. It can provide 2D FO, 2.xD FO, FO PoP, FCPLP, and other advanced system integration packaging.

Tianxin Interconnect Technology Co., Ltd. is a wholly-owned subsidiary of Shenzhen Nan Electronics. Tianxin Interconnect relies on the System-in-Package (SiP) and Panel-level Fan-out Package (FOPLP) platform to provide customers with highly integrated, miniaturized semiconductor device module packaging solutions and semiconductor test interface solutions. The products are widely used in high-end medical, industrial control, communication, semiconductor testing, and other fields. The company has R&D teams and manufacturing plants in Shenzhen and Wuxi, providing customers with one-stop services such as solution evaluation, design simulation, and packaging testing. Tianxin Interconnect Technology Co., Ltd. Wuxi Branch is currently conducting research on fan-out wafer-level packaging technology.

Zhongke Sihe is also committed to building a panel-level power chip fan-out packaging process manufacturing platform, and based on this platform, it carries out research on advanced Fan-out packaging process technology and power chip/module product research. It develops, manufactures, and sells new types of high-density power chip/modules for various fields such as consumer electronics, industrial control, automotive electronics, communication/server, and medical, covering product types such as TVS, MOSFET, SBD, Bridge, DC-DC, IPM, and other devices and modules. Currently, Zhongke Sihe has mass-produced DFN-type TVS products based on panel-level fan-out packaging. This series of TVS products has been applied in large quantities in terminal brands such as Xiaomi, Haier, and Hisense.Handicaps and Opportunities

It is still important to note that FOPLP (Fan-Out Panel Level Packaging) needs to develop comprehensively, and there are still many constraints to be overcome. The process of achieving this technology involves a variety of equipment and technical challenges, facing multiple challenges such as precision, efficiency, and speed. Among them, the lack of standardization in panel size and assembly process is the biggest obstacle to the application of FOPLP. At the same time, although the packaging size of FOPLP is large, the yield rate is still not as good as FOWLP (Fan-Out Wafer Level Packaging), so improving the yield rate is also a focus of its development.

In the future, with the continuous maturity and improvement of FOPLP technology, and more manufacturers from different fields joining this camp, the fan-out packaging technology is expected to gradually mature and become popular.

According to the Fan-Out Packaging Market Report released by Yole Intelligence in 2023, the FOPLP market size will rapidly expand from $41 million in 2022, and is expected to grow at a compound annual growth rate of 32.5% to $221 million by 2028.

At the same time, the market share of FOPLP in the FOWLP market will also rise from 2% in 2022 to 8% in 2028.

In the near future, FOPLP will welcome a moment of comprehensive explosion with its unique advantages.

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