Rapidus plans to add chip packaging services in its 2nm wafer fab.
With Intel joining the wafer foundry game, this niche market has become quite competitive again. This is the niche market that Rapidus, a foundry startup supported by the Japanese government and several large Japanese companies, will enter in 2027, with its first wafer fab coming online a few years later.
In the latest update on the company's first leading-edge wafer fab, Rapidus revealed that they also intend to enter the chip packaging game. Once completed, this 5 trillion yen ($32 billion) wafer fab will offer chip lithography technology at the 2nm node and provide packaging services for chips produced within the facility — in this industry, if packaging is not fully outsourced (OSAT), it is usually handled in a dedicated facility.
Ultimately, while the company hopes to provide services to the same clients as TSMC, Samsung, and Intel foundries, the company plans to do something almost completely different from its competitors to speed up the pace of chip manufacturing from the completion of design to obtaining working chips from the wafer fab.
Henri Richard, General Manager and President of Rapidus USA, said: "I know some people may think that Japan is known for quality and attention to detail, but not necessarily for speed or flexibility. But I will tell you that Atsuyoshi Koike (the head of Rapidus) is a very special executive. That is to say, he has all the qualities of Japan, with a lot of American thinking. Therefore, he is a very unique person, and of course, very focused on creating a very flexible and very fast-moving company."
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Perhaps the most significant difference between Rapidus and traditional foundries is that the company will only provide leading manufacturing technology to customers: 2nm in 2027 (Phase 1) and 1.4nm in the future (Phase 2). This is in stark contrast to other wafer foundries, including Intel, which tend to provide customers with a full range of manufacturing processes to attract more customers and produce more chips. Obviously, Rapidus hopes that there will be enough Japanese and American chip developers who are willing to use its 2nm manufacturing process to produce their designs. That being said, the number of chip designers using the most advanced process node at any given time is relatively small — limited to large companies that need a first-mover advantage and have the profits to justify taking risks — so whether Rapidus's business model will be successful remains to be seen. The company believes it will, because the market for chips manufactured at advanced nodes is growing rapidly.
Richard said: "Until recently, IDC estimated the market for 2nm and below to be about $80 billion, and I think we will soon see a revision of potential to $150 billion. TSMC is the leader in this field. Samsung is there, and Intel will enter this field. But the market is growing so much, and the demand is so high, that Rapidus's success does not require much market share. One thing that makes me feel very relieved is that when I talk to our EDA partners, when I talk to our potential customers, it is clear that the entire industry is looking for alternative supply from a completely independent foundry. Samsung has a place in this industry, and Intel has a place in this industry, which is currently owned by TSMC. However, another completely independent foundry is welcomed by all ecosystem partners and customers. So, I feel very good about Rapidus's positioning."When it comes to advanced process technology, it is worth noting that Rapidus does not plan to use ASML's High-NA Twinscan EXE lithography scanner for 2nm production. Instead, Rapidus insists on using ASML's tried-and-tested low numerical aperture (NA) scanner, which will reduce the cost of Rapidus's wafer fab, although this will require the use of EUV double patterning, which will increase costs and extend the production cycle in other ways. Even with these trade-offs, SemiAnalysis analysts believe that low NA double patterning may be more economically feasible considering the cost of high NA EUV lithography tools and the halving of the imaging field.
Richard said: "We believe we are very satisfied with our current 2nm (low NA EUV) solution, but we may consider a different solution at 1.4nm."
At present, only Intel plans to use high NA tools to manufacture chips on its 14A (1.4-nanometer) manufacturing process. TSMC and Samsung Foundry appear to be more cautious, so Rapidus is not the only company that is cautious about high NA EUV tools.
Advanced packaging in advanced wafer fabs
In addition to advanced process technology, high-end chip designers (such as those for AI and HPC applications) also need advanced packaging technology (such as for HBM integration), and Rapidus is also ready to provide these technologies. The difference between the company and its peers is that it plans to manufacture and package chips in the same wafer fab.
"We intend to use the backend capabilities of the Hokkaido wafer fab as a differentiating factor," Richard said. "I believe our advantage lies in starting from scratch and being able to build the industry's first fully integrated front-end and back-end semiconductor wafer fab. Others will modify and adapt their existing capabilities, but we have a blank slate, and part of the secret that Koike's son brings to Rapidus is some very interesting ideas on how to integrate the front end and back end."
Intel, Samsung, and TSMC have separate chip manufacturing and packaging facilities because even the most complex packaging methods involving silicon interposers cannot match the complexity of modern processors. The tools used to build silicon interposers and the equipment used to manufacture full-logic chips are very different, so it usually makes little sense to install them in the same cleanroom because they do not complement each other well.
On the other hand, transporting wafers from one location to another is a time-consuming and risky task, so integrating everything into one campus may make sense because it greatly simplifies the supply chain.
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